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iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 1/30 FEATURES o Programmable angle resolution from 1 to 256 steps per period o Interpolation factors from x0.25 to x64 o Input frequency to 115 kHz with x64, to 230 kHz with x32, to 460 kHz with x16 o Latency of less than 1 s o Selectable gain permits single-ended and differential input signals from 10 mV to 1.5 V peak-peak o Index gating input with fine adjustable offset o Programmable index pulse output position and width o Four incremental output modes: quadrature encoder with index, up/down clock, increment/direction, 3 phase commutation o Programmable filter and hysteresis o Direct sensor connection, minimized count of external components o Non-volatile setup due to internal EEPROM o Fully re-programmable via serial 1- and 2-wire interfaces o Power-on reset circuit and on-chip oscillator o ESD protection and TTL-/CMOS-compatible outputs APPLICATIONS o Interpolation IC for position data acquisition from analog sine/cosine sensors o Optical linear and rotary encoders o Magneto resistive sensors and encoders
PACKAGES
QFN24
BLOCK DIAGRAM
VDDA PINA
+
NRST
VDD CLKSEL
-
POWERON RESET
SYSTEM CLOCK
CLKEXT
-
NINA
+
iC-TW2
B_V NB_NV A_U
PINB
+
NA_NU
-
Z_W
SIN/D CONVERSION
NZ_NW
NINB
+
FILTER
SDAT
PINZ
+ HYSTERESIS SIGNAL PROCESSING ABZ- / UVWGENERATOR 1W-/2WINTERFACE
SCLK
-
1W
Zin
NINZ
+ INDEX ENABLE
REGISTERS INTERNAL EEPROM
BANDGAP
VC GND
GNDA
Copyright (c) 2010 iC-Haus
http://www.ichaus.com
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 2/30 DESCRIPTION iC-TW2's interpolation engine accepts two fully differential sensor bridges delivering sinusoidal input signals (SIN/COS) to produce a highly interpolated output signal. No further external components are required. Single ended sensor signals are supported by tying the negative input terminal to a signal reference, usually VDD/2. iC-TW2 generates one index pulse for every input period. The position in respect to the start of the period as well as the width of the pulse is fully programmable. Index pulse position can be used in conjunction with the startup mode to guarantee a desired phase relationship between A, B and index output pulse. There are four different output modes provided, including 3-phase commutation output for brushless DC motors. It is highly programmable to meet requirements for a wide range of applications. Two serial interfaces have been included to permit configuration of the device, also accessing an internal EEPROM. Both interfaces allow complete configuration of the device including transfer of setup and system data to register and EEPROM for non-volatile configuration. For an illustration of the interpolation function of the iC-TW2 see Figure 2 on page 10.
CONTENTS PACKAGES ABSOLUTE MAXIMUM RATINGS THERMAL DATA ELECTRICAL CHARACTERISTICS REGISTER MAP PROGRAMMING DESCRIPTION OF INTERPOLATION Interpolation vs. Resolution . . . . . . . . . . INPUT STAGE OUTPUT MODES AB Quadrature And Up/Down and Incr/Dir Modes . . . . . . . . . . . . . . . . . . . 3 Phase Commutation Mode . . . . . . . . . INDEX GATING CALIBRATION A/B gain and offset calibration . . . . . . . . . Oscillator and index window calibration . . . 3 4 4 5 START UP 8 9 10 10 11 12 13 14 15 17 17 17 Power-On-Reset . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . 1W- / 2W-INTERFACE AND EEPROM ACCESS Memory map . . . . . . . . . . . . . . . . . . 2W-Interface . . . . . . . . . . . . . . . . . . 2W-Interface timing . . . . . . . . . . . . . . . 1W-Interface . . . . . . . . . . . . . . . . . . 1W-Interface write sequence . . . . . . . . . Writing the register bank to the EEPROM . . TEST MODES Production test control bits . . . . . . . . . . TYPICAL APPLICATIONS PCB LAYOUT GUIDELINES 21 21 21 22 22 22 24 26 26 26 27 27 28 29 CONFIGURATION DEPENDENCIES Selecting configuration parameters . . . . . . Clock tuning . . . . . . . . . . . . . . . . . . . DEVICE IDENTIFICATION 19 19 19 20
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 3/30 PACKAGES PIN CONFIGURATION QFN24 4 mm x 4 mm PIN FUNCTIONS No. Name Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TP VDD B_V NB_NV A_U NA_NU GND NZ_NW Z_W 1W VDDA GNDA n.c. PINB NINB CLKSEL NRST NINA PINA VC NINZ PINZ SCLK CLKEXT SDAT +3 V to +5.5 V Digital Supply Voltage B Signal / V Signal Output Inverted B / Inverted V Signal Output A Signal / U Signal Output Inverted A / Inverted U Signal Output Digital Ground Inverted Z / Inverted W Signal Output Z Signal / W Signal Output 1W-Interface, signal input +3 V to +5.5 V Analog Supply Voltage Analog Ground Pin not connected Signal Input B+ Signal Input BSystem Clock Selection Input External Reset Input (active low) Signal Input ASignal Input A+ 1.2 V Reference Voltage Output Signal Input Z- (Index) Signal Input Z+ (Index) 2-Wire Interface, clock input External Clock Input 2-Wire Interface, serial data in/out Thermal Pad (bottom side)
The Thermal Pad of the QFN package (bottom side) is to be connected to a ground plane on the PCB which must have GND potential. GNDA must be wired to GND. Only pin 1 marking on top or bottom defines the package orientation (iC-TW2 label and coding is subject to change).
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 4/30 ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur. Item No. Symbol Parameter Supply Voltage VDD, VDDA Supply Voltage Difference VDD vs. VDDA Conditions Min. referenced to GND VDDA = VDD - VDDA -0.3 0 -0.3 Max. 6.0 0.5 VDD + 0.5 V V V V Unit
G001 VDD, VDDA G002 VDDA G003 V()
Voltage at referenced to GND PINA, NINA, PINB, NINB, PINZ, NINZ, B_V, NB_V, A_U, NA_U, Z_W, NZ_W, 1W, SDAT, SCLK, CLKSEL, CLKEXT Current in PINA, NINA, PINB, NINB, PINZ, NINZ, B_V, NB_V, A_U, NA_U, Z_W, NZ_W, 1W, SDAT, SCLK, CLKSEL, CLKEXT, VC ESD Susceptibility Of Signal Outputs ESD Susceptibility (remaining pins) Junction Temperature Storage Temperature HBM, 100 pF discharged through 1.5 k; pins A_U, NA_U, B_V, NB_V, Z_W, NZ_W HBM, 100 pF discharged through 1.5 k
G004 I()
-20
20
mA
G005 Vd G006 Vd G007 Tj G008 Ts
1.5 1 -40 -40 125 125
kV kV C C
THERMAL DATA
Item No. T01 T02 Symbol Ta Rthja Parameter Operating Ambient Temperature Thermal Resistance Chip To Ambient QFN24 surface mounted to PCB, following JEDEC 51 Conditions Min. -40 32 Typ. Max. 125 C K/W Unit
All voltages are referenced to ground unless otherwise stated. All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 5/30 ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = VDDA = 3.0...5.5 V, Tj = -40...125 C, unless otherwise stated Item No. 001 002 Symbol Parameter Conditions Min. VDD, VDDA I(VDD, VDDA) Permissible Supply Voltage VDD, VDDA Total Supply Current VDD = 3.3 V at 0 Hz VDD = 3.3 V at 100 kHz VDD = 5.5 V at 0 Hz VDD = 5.5 V at 100 kHz Vc()hi = V() - VDD; I() = 10 mA I() = -10 mA 0.5 -1.1 1.4 6.0 -1.0 0.7 -0.3 0.85 -15 -10 13 -40 INTER = 1 . . . 64, FREQ = 0 INTER = 1 . . . 64, FREQ = 1 INTER = 1 . . . 64, FREQ = 2 . . . 127 INTER = 17 . . . 128, FREQ = 0 INTER = 17 . . . 128, FREQ = 1 . . . 127 INTER = 129 . . . 255 INTER = 0 VDD = 3.0 V, Tj = 25 C, CLOCK = 0 VDD = 3.0 V, Tj = 25 C, CLOCK = 31 VDD = 5.5 V, Tj = 25 C, CLOCK = 0 VDD = 5.5 V, Tj = 25 C, CLOCK = 31 VDD = 3.6 V, Tj = 25 C VDD = 5.5 V, Tj = 25 C over temperature range -40 C to 125 C over supply voltage range 3.0 V to 5.5 V Tj = 125 C Tj = 85 C Tj = 25 C -20 0 10 100 1000 106 CL = 100 nF, I(VC) = 0 mA VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % V() = 0...VDD - 1 V Vpu() = VDD - V(), I() = -3 A 1.15 1.5 3.3 0.8 1.0 -3 500 1.21 1.27 V V V V V A mV 64 128 256 128 256 256 256 25 35 28 40 25 30 0 25 MHz MHz MHz MHz MHz MHz % % years years 40 0.3 1.15 15 10 mV mV mV mV 3.5 3.0 Typ. Max. 5.5 5 20 8 40 1.2 -0.3 VDD 1.2 V mA mA mA mA V V V dB dB dB dB Unit
Total Device
003 004 101 102 103 104 105 106 107 108 109 110 111
Vc()hi Vc()lo Vin()sig Step(GC) Step(GF) CGM Vin()os
Clamp-Voltage hi at all pins Clamp-Voltage lo at all pins Permissible Input Voltage Range Nominal Coarse Gain Step Size Nominal Fine Gain Step Size Gain Matching G(CHA)/G(CHB) Input Referred Offset Voltage
Input Amplifier PINA, NINA, PINB, NINB
AGabs(GC) Coarse Gain Absolute Accuracy AGabs(GF) Fine Gain Absolute Accuracy
Vout()ossc Output Referred Offset Correction Step Accuracy Step(OFSx) Nominal Offset Correction Step Size Vout()os FR Output Referred Offset Voltage Permissible Input Frequency; Frequency Ratio FR = fcal / fin
Oscillator 201 fosc
Frequency Tuning Range
202 203 204
fcal dfosc (T) dfosc (V)
User Calibrated Frequency fosc Frequency Variation Frequency Variation Data Retention Time Number of Erase/Write Cycles Number of Read Cycles Reference Voltage
EEPROM 301 Tret 302 303 401 Ncycles Nread Vref(VC)
Reference Voltage Output VC Digital Inputs NRST 501 Vt()hi Input Threshold Voltage hi 502 503 504 Vt()lo Ipu() Vpu() Input Threshold Voltage lo Input Pull-up Current Input Pull-up Voltage
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 6/30 ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = VDDA = 3.0...5.5 V, Tj = -40...125 C, unless otherwise stated Item No. Symbol Parameter Conditions Min. VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % V() = 1 V...VDD I() = 3 A 4 500 1.5 3.3 0.8 1.0 Typ. Max. V V V V A mV Unit
Digital Inputs CLKSEL, CLKEXT 601 Vt()hi Input Threshold Voltage hi 602 603 604 Vt()lo Ipd() Vpd() Input Threshold Voltage lo Input Pull-down Current Input Pull-down Voltage
Digital Outputs A_U, NA_NU, B_V, NB_NV, Z_W, NZ_NW 701 Vs()hi Output Saturation Voltage hi Vs()hi = V(VDD) - V(), I() = -6 mA; VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % 702 703 Isc()hi Vs()lo Short-circuit Current hi Output Saturation Voltage lo V() = GND I() = 6 mA; VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % V() = VDD VDD = 3.0 V, CL() = 10 pF VDD = 3.0 V, CL() = 10 pF source and sink referred to period T, see Fig. 1 referred to period T, see Fig. 1 see Fig. 1 referred to 360 input signal GC(2:0) = 1 INTER(7:0) = 0 FREQ(6:0) = 127 f() < 50 Hz referred to period of A, B GC(2:0) = 1 INTER(7:0) = 0 FREQ(6:0) = 127 f() < 50 Hz -6 -10 50 25 1/ fcore 20 -100
0.5 0.4 -15 0.3 0.25 140 4 4 10
V V mA V V mA ns ns mA % %
704 705 706 707 708 709 710
Isc()lo tr() tf() I()max twhi tAB tMTD
Short-circuit Current lo Output Rise time Output Fall Time Permissible Load Current Duty Cycle at Output A, B Output Phase A vs. B Minimum Transition Distance
Signal Processing 801 AAabs Absolute Angular Accuracy
6
DEG
802
AArel
Relative Angular Accuracy
-20
20
%
803
ABrel
Relative Angular Accuracy A vs. B Permissible Input Voltage Range Input Referred Offset Voltage Comparator Offset Step Size OFSZ = 0..7 OFSZ = 8..15 0.0 -15
1/2 AArel VDD +15 1.5 -1.5 1.8 20
%
Index Comparator PINZ, NINZ 901 902 903 Vin()sig Vin()os Vin()step V mV mV mV V ms
Power-Down-Reset A01 A02 VDDon tbusy()cfg Turn-on Threshold VDD (power on release) Duration of Startup Configuration
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 7/30 ELECTRICAL CHARACTERISTICS
Operating conditions: VDD = VDDA = 3.0...5.5 V, Tj = -40...125 C, unless otherwise stated Item No. Symbol Parameter Conditions Min. VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % V() = 1 V...VDD I() = 3 A I() = 2 mA Vs()hi = VDD - V(); I() = -2 mA 3 -2.5 scales with oscillator frequency timing, see Table 32 scales with oscillator frequency timing, see Table 32 VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % VDD = 3.3 V +/- 10 % VDD = 5.0 V +/- 10 % V() = 0...VDD - 1 V Vpu() = VDD - V(), I() = -3 A 1.5 3.3 0.8 1.0 -3 500 1.25 20 4 500 450 700 1.5 3.3 0.8 1.0 Typ. Max. V V V V A mV mV mV mA mA MHz ms Unit
2-Wire Interface SDAT, SCLK B01 Vt()hi Input Threshold Voltage hi B02 B03 B04 B05 B06 B07 B08 B09 B10 Vt()lo Ipd() Vpd() Vs()lo Vs()hi Isc()lo Isc()hi Input Threshold Voltage lo Input Pull-down Current Input Pull-down Voltage Saturation Voltage lo at SDAT Saturation Voltage hi at SDAT Short-circuit Current lo at SDAT Short-circuit Current hi at SDAT
fclk(SCLK) Permissible Clock Frequency SCLK tbusy()e2p Max. Duration of EEPROM access
1-Wire Interface 1W C01 Vt()hi Input Threshold Voltage hi C02 Vt()lo C03 Ipu() C04 Vpu() Input Threshold Voltage lo Input Pull-up Current Input Pull-up Voltage
V V V V A mV
tAB
tMTD
B
twhi
A
twhi AArel T
Figure 1: Relative phase distance
AArel
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 8/30 REGISTER MAP
Register Map Adr
0x00
Bit 7
Bit 6
Bit 5 IDA(3:0)
Bit 4
Bit 3
Bit 2
Bit 1 IDB(3:0)
Bit 0
Device Indentification Operating Modes
0x01 RESET (P. 21) CALIB1 (P. 17)
STARTUP(1:0)(P. 21) INTER(7:0)(P. 12) IPOS(7:0)(P. 13) IWIDTH(7:0)(P. 13)
DIR (P. 12)
MODE(1:0)(P. 12)
Interpolation Rate
0x02
Index Position
0x03
Index Width
0x04
Conversion Settings
0x05 0x06 GRANULAR(P. 27)
FREQ(6:0)(P. 20) FILTER(1:0)(P. 20) GFB(1:0) (P. 11) GFA(1:0) (P. 11) OFSA(5:0)(P. 11) OFSB(5:0)(P. 11) HYST(1:0)(P. 20) GC(2:0) (P. 11)
Gain and Offset
0x07 0x08 0x09
Bias and Oscillator Trimming
0x0A
VC(1:0)(P. 27) OFSZ(3:0)(P. 17)
CLOCK(4:0)(P. 17)
EN_MON (P. 27) CLKDLY (P. 27) CLKDIV (P. 20) CLKMODE
(P. 27)
Index Computation and Miscellaneous
0x0B
Reserved and Calibration
0x0C 0x0D
Reserved(P. 27) Reserved(P. 27)
EE_READ
(P. 27)
CALIB2
EEPROM Control
0x0E EE_WRITE
(P. 26)
Reserved(P. 27)
Test Register
0x0F
MONITOR(7:0)(P. 27) Table 4: Register Map
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 9/30 PROGRAMMING Input Stage GC: GFA/B: OFSA/B: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 11 Coarse gain control (P. 11) Fine gain control on channel A/B (P. 11) Offset control on channel A/B (P. 11) Device Identification . . . . . . . . . . . . . . . . . . . . . . . Page 20 IDA: Major Device Revision (P. 20) IDB: Minor Device Revision (P. 20) Start Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 21 STARTUP: Startup sequence selection (P. 21) RESET: Restart interpolation engine (P. 21) 1W- / 2-W-Interface And EEPROM Access . Page 22 EE_WRITE: EEPROM store command (P. 26) Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 27 GRANULAR: A/B output edge granularity control (P. 27) VC: Reference voltage fine tuning (P. 27) CLKMODE: Clock source selection (P. 27) CLKDLY: Clock distribution delay line selection (P. 27) EN_MON: Position data monitor control (P. 27) MONITOR: Monitor register (P. 27) EE_READ: EEPROM read command (P. 27)
Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 12 MODE: Output mode selection (P. 12) DIR: Count direction (P. 12) INTER: Interpolation rate selection (P. 12) IPOS: Index pulse position (P. 13) IWIDTH: Index pulse width selection (P. 13) Index Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 15 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17 CALIB1: Calibration mode 1 select (P. 17) CALIB2: Calibration mode 2 select (P. 17) OFSZ: Index comparator offset control (P. 17) CLOCK: Oscillator tune (P. 17) Configuration Dependencies . . . . . . . . . . . . . . Page 19 FREQ: Maximum input frequency (P. 20) CLKDIV: Master clock divider (P. 20) HYST: Hysteresis control (P. 20) FILTER: Datapath filter control (P. 20)
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 10/30 DESCRIPTION OF INTERPOLATION iC-TW2 is a monolithic A/D converter which converts sine/cosine sensor signals with a selectable resolution and hysteresis into angle position data. The interpolation function is shown in Figure 2.
Gain channel B GC(2:0) and GFB(1:0)
Gain channel A GC(2:0) and GFA(1:0) Offset channel A OFSA(5:0) Offset channel B OFSB(5:0)
PINB
PINA
A_U B_V Index pulse position IPOS(7:0) PINZ Z_W Index pulse is disabled through pin PINZ low
Figure 2: Interpolating function Interpolation vs. Resolution There is a difference between interpolation factor and resolution. Resolution (interpolation rate) is determined by the sum of edges at the incremental outputs (AB quadrature output) within one input signal period . polation factor. The interpolation factor equals to the the resolution divided by 4.
Interpolation INTER(7:0) (Interpolation of x5 shown)
Index pulse width IWIDTH(7:0)
Dividing the resolution by the existing edges of the SINE and COSINE signals ( = 4 ) equals to the inter-
Example: An interpolation factor of x8 brings a resolution of 32 (edges). To operate with a interpolation factor of 8 configure INTER(7:0) to 32.
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 11/30 INPUT STAGE A programmable gain amplifier (PGA) with output referred offset adjustment is used as input stage, shown in Figure 3. The coarse gain is common for both channel A and B and is programmed through register GC(2:0). Table 5 shows the required gain setting for a given input signal amplitude (peak to peak, differential). Fine tuning gain is applied individually to channel A and B by programming registers GFA(1:0) and GFB(1:0) respectively.
OFSA(5:0) OFSB(5:0) Code 111111 111110 100001 100000 000000 000001 011110 011111 Addr. 0x08; bit 5:0 Addr. 0x09; bit 5:0 Function, defaults to eeprom setting maximum negative adjust: -403 mV -390 mV -13 mV no correction no correction 13 mV 390 mV maximum positive adjust: 403 mV R/W R/W
GC(2:0) Code 000 001 010 011 100 101 110 111
Addr. 0x07; bit 2:0 Function, defaults to eeprom setting 1.5 V - 800 mV 800 mV - 400 mV 400 mV - 200 mV 200 mV - 100 mV 100 mV - 50 mV 50 mV - 25 mV 25 mV - 10 mV not defined
R/W
Table 7: Offset control of channel A/B Consider Table 8 regarding the relationship between input signal peak-peak differential amplitude, amplifier gain setting and resulting offset correction range.
Input amplifier gain and offset Input signal range Register Input GC(2:0) referred offset step size 800 mV - 1.5 V 400 mV - 800 mV 0 1 2 3 4 5 6 26 mV 13 mV 6.5 mV 3.25 mV 1.63 mV 0.81 mV 0.41 mV
Table 5: Coarse gain control of channel A/B
Input referred offset range 806 mV 403 mV 202 mV 101 mV 50 mV 25 mV 12.6 mV
GFA(1:0) GFB(1:0) Code 00 01 10 11
Addr. 0x07; bit 4:3 Addr. 0x07; bit 6:5 Function, defaults to eeprom setting 0 dB 0.7 dB 1.4 dB 2.1 dB
R/W R/W
200 mV - 400 mV 100 mV - 200 mV 50 mV - 100 mV 25 mV - 50 mV 10 mV - 25 mV
Table 8: Input amplifier gain and offset
Input amplifier OFSB(5:0) GFB(1:0)
Table 6: Fine gain control of channel A/B
PINB
+
Offset adjustment is provided at the output of the input amplifier. It is individually programmed through register OFSA(5:0) and OFSB(5:0). Adjustment is made in steps of 13 mV and the corresponding register values are sign magnitude encoded. Input referred offset becomes gain dependent and is defined as follows:
+
GC(2:0)
Xb
NINB PINA NINA
to interpolation engine
+
-
+
GFA(1:0) OFSA(5:0)
Xa
OFSAinput_referred =
13 mV OFSA(5 : 0) GC(2 : 0)
Figure 3: Input stage
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 12/30 OUTPUT MODES The iC-TW2 provides four different output modes, which are configured by programming bits MODE(1:0) of register 0x01. Modes 0, 1 and 2 are incremental modes whereas mode 3 is a 3-phase commutation output for brushless DC motors. Consider Figure 4 for a comparison of the 3 incremental output modes.
MODE(1:0) Addr. 0x01; bit 1:0 Code Function, defaults to eeprom setting 00 01 10 11 AB quadrature mode 0 up / dn mode 1 inc / dir mode 2 3 phase commutation mode 3 R/W INTER (7:0) Code Adr 0x02, Bit 7:0 R/W STEP Angle Steps Per Period 256 1 2 3 4 5 ... 60 61 62 63 64 65 66 67 68 69 ... 124 125 126 127 128 129 130 131 132 133 ... 250 251 252 253 254 255 IPF Interpolation Factor 64 0.25 0.5 0.75 1 1.25 ... 15 15.25 15.5 15.75 16 16.25 16.5 16.75 17 17.25 ... 31 31.25 31.5 31.75 32 32.25 32.5 32.75 33 33.25 ... 62.5 62.75 63 63.25 63.5 63.75 fin()max Maximum Permissible Input Frequency * 115 kHz ** 460 kHz 460 kHz 460 kHz 460 kHz 460 kHz 460 kHz 460 kHz 460 kHz 460 kHz 460 kHz 460 kHz 230 kHz 230 kHz 230 kHz 230 kHz 230 kHz 230 kHz 230 kHz 230 kHz 230 kHz 230 kHz 230 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz 115 kHz
0x00 0x01 0x02 0x03 0x04 0x05 ... 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 ... 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x82 0x83 0x84 0x85 ... 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF
Table 9: Output mode selection In increment / direction mode the count direction can be inverted via control bit DIR of register 0x01.
DIR Code 0 1 Addr. 0x01; bit 2 Function, defaults to eeprom setting Normal count direction Inverted count direction R/W
Table 10: Count direction selection
Table 11: Converter resolution
*
Depending on configuration FREQ = 0, CLKDIV = 0 and fcal = 920 kHz.
**
Maximum permissible input frequency for commutation operation (mode = 3) .
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 13/30 AB Quadrature And Up/Down and Incr/Dir Modes
Sensor position A_U A/B mode 0 B_V up / dn A_U mode 1 B_V inc / dir A_U mode 2 B_V
0
1
2
3
4
5
6
5
4
3
2
Figure 4: Incremental output modes (mode 0, 1, 2)
IPOS(7:0) Code 0 1 2 ... Addr. 0x03; bit 7:0 Function, defaults to eeprom setting No offset 1 increment offset 2 increments offset ... Index pulse will shifted by IWIDTH(7:0) increments. Programmed value is within the range of 0 to INTER(7:0) - 1. ... 255 increments offset A fixed phase relation to A/B is guaranteed only with STARTUP(1:0) = 0b10 ('ABSOLUTE") or STARTUP(1:0) = 0b11 ('BURST"). R/W IWIDTH(7:0) Code 0 1 2 ... Any other value n Addr. 0x04; bit 7:0 Function, defaults to eeprom setting disable pulse generation 1 increment width 2 increments width ... Index pulse will extend over IWIDTH(7:0) increments. Programmed value is within the range of 0 to INTER(7:0) - 1. ... 255 increments width R/W
... 255 Note:
... 255
Table 13: Index pulse width selection
Table 12: Index pulse position
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 14/30 3 Phase Commutation Mode The 3 phase commutation output (mode 3) is shown in Figure 5. It is important that register INTER(7:0) is programmed with the value 0x00 in order for the commutation mode to work. The mode = 3 requires an internal interpolation INTER(7:0) of 256. Register IPOS(7:0) is used to accurately position the commutation. IWIDTH(7:4) and IWIDTH(3:0) is subsequently used to fine tune V and W in respect to U. All used offsets within the commutation mode (mode 3) as are IPOS(7:0), IWIDTH(3:0) and IWIDTH(7:4) operate in this step width of 1.4 . There is no other pole count commutation possible to configure as the described 3 phase commutation.
IWIDTH(3:0) Addr. 0x04; bit 3:0 Code V output offset, defaults to eeprom setting 0111 ... 0010 0001 0000 1111 1110 ... 1111 9.84 ... 2.81 1.40 0 -1.40 -2.81 ... 11.25 R/W
Table 15: V commutation signal position offset
IWIDTH(7:4) Addr. 0x04; bit 7:4 Code W output offset, defaults to eeprom setting 0111 ... 0010 9.84 ... 2.81 1.40 0 -1.40 -2.81 ... 11.25 R/W
0
IPOS (7:0)
120
240
0
A_U B_V Z_W
IWIDTH (3:0) IWIDTH (7:4)
Figure 5: 3-Phase commutation output (mode 3)
IPOS(7:0) Code 0 1 2 ... Addr. 0x03; bit 7:0 Function, defaults to eeprom setting 0 1.40 2.81 ... Programmed value is within the range of 0 to INTER(7:0) - 1. ... 358,59 R/W
0001 0000 1111 1110 ... 1111
Table 16: W commutation signal position offset
... 255
Table 14: UVW commutation signal position offset
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 15/30 INDEX GATING The iC-TW2 can interface to a wide range of index gating sources. Most commonly used are the digital hall sensor and the MR sensor bridge. The digital Hall sensor provides a large swing input signal to the iC-TW2. Depending on the polarity of the Hall it is either connected to pin NINZ or PINZ. Most Hall sensors use an open drain stage pulling the output low in the presence of a magnetic field. The unused terminal PINZ or NINZ should be biased to an adequate mid voltage level to guarantee good noise margin. The iC-TW2 provides a constant 1.21 V at pin VC that can be used for this purpose (refer to Figure 6).

Figure 7: MR sensor index configuration

Index gating should be calibrated at SIN/COS input frequencies below 5 kHz to minimize the effect of latency. Timings shown in Table 17 are valid for input frequencies below 5 kHz and fsystem of 25 MHz. Once the timings are satisfied according to Table 17, correct operation is guaranteed up to the maximum input frequency as specified in Table 22 on page 19.
Parameter tsetup Description Index window setup time before rising edge of Z_W Index window hold time after falling edge of Z_W Condition * no filter 8 average 16 average no filter 8 average 16 average min 0.4 s 0.5 s 0.7 s 0.4 s 0.5 s 0.7 s
Figure 6: Digital Hall sensor index configuration An MR sensor differential bridge can also be used to gate the index. Typically, the MR sensor provides a small signal amplitude. In addition, residual side lobes are present that can trigger double indexing. The iCTW2 provides offset control capability to fine tune the threshold voltage of the index comparator. This greatly simplifies end product calibration as variation in sensor offset can be compensated for. Figure 8 shows a correctly set threshold when using an MR gating sensor. The side lobes are below the threshold line and no parasitic triggering occurs.
thold
* Filter register FILTER(1:0) fsystem = 25 MHz, all timings scale with fsystem Refer to Table 22 for more information
Table 17: Index gating and timing
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 16/30
MR Sensor pin PINZ
Input Z threshold OFSZ(3:0)
index window pin A_U pin B_V tsetup pin Z_W
Figure 8: Index gating
Chip internal index window. This signal can be observed by enabling calibration mode 2 (bit CALIB2)
thold Index position and index width. IPOS(7:0) and IWIDTH(7:0)
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 17/30 CALIBRATION In order to facilitate system gain and offset calibration, two calibration modes can be enabled by either setting bit CALIB1 of register 0x01 or CALIB2 of register 0x0C.
CALIB2 CALIB1 CALIB2;1 00 01 10 11 Addr. 0x0C; bit 0 Addr. 0x01; bit 5 Function, defaults to eeprom setting Normal operation, no calibration A/B gain and index calbration Oscillator and index window calibration Not permitted R/W R/W
Oscillator and index window calibration When calibration mode 2 is enabled, the output of the index comparator is driven on pin B_V. In conjunction with the actual index output on pin Z_W, the gating window can be centered around the output pulse. Fine offset adjustment applied to the input of the index comparator is possible through OFSZ(3:0) which is sign magnitude encoded. This is beneficial when using small amplitude index sources such as an MR sensor. Simultaneously, the oscillator frequency fosc /32 can be observed on pin A_U. Register CLOCK(4:0) is used to tune the oscillator to its desired frequency.
OFSZ(3:0) Code 1111 1110 1001 ... 1000 0000 0001 ... 0110 0111 1 Addr. 0x0B; bit 7:4 Function, defaults to eeprom setting maximum negative adjust, -10.5 mV -9 mV -1.5 mV ... no correction no correction 1.5 mV ... 9 mV 10.5 mV calibration mode 2 activated R/W
Table 18: Calibration mode A/B gain and offset calibration In calibration mode 1 the SIN/COS input is directly passed through two zero-cross comparators to output pin A and B respectively. In addition, the sum of the input signals SIN + COS 2 is also fed through a comparator and driven on pin Z. The actual calibration process must be carried out in several steps. 1. Select proper coarse gain by programming register GC(2:0). Set GFA(1:0) and GFB(1:0) to 0. 2. Adjust offset register OFSA(5:0) and OFSB(5:0) until output A and B are 50% duty cycle. 3. Adjust fine gain register GFA(1:0) and GFB(1:0) until output Z is equidistant between output A and B. 4. Repeat step 1 and 2 until no more improvement can be achieved.
Table 19: Index comparator offset control
CLOCK(4:0) Addr. 0x0A; bit 4:0 Code Function, defaults to eeprom setting 00000 ... 11111 Slowest clock ... fastest clock R/W
Table 20: Oscillator tuning
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 18/30
PINB
(A+B) / sqrt(2) PINA
A_U B_V Z_W
Figure 9: Calibration of A/B gain and offset
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 19/30 CONFIGURATION DEPENDENCIES The following paragraph describes dependencies between several chip configuration settings and system performance. It is vital to understand the implication of system parameters to be able to tune the iC-TW2 for full performance. It is especially important to correctly program register FREQ(6:0), since this directly affects accuracy and maximum allowed input frequency. Selecting configuration parameters Follow the outlined procedure below to select the proper configuration. Refer to Table 22 for reference. 1. Determine the maximum input frequency finput as required by the application. 2. Calculate fcore based on finput and interpolation rate INTER(7:0). 3. Select fsystem based on the accuracy requirement. See Table 21. Accuracy is a function of interpolation and frequency (registers INTER(7:0) and FREQ(6:0)).
INTER(7:0) 129 to 256; 0 65 to 128 1 to 64 FREQ(6:0) 0 to 127 0 1 to 127 0 1 2 to 127
Always use the highest accuracy possible to still satisfy finput . 4. Determine fosc . Selecting the slowest fosc possible lowers power consumption and improves jitter performance. Clock tuning 1. Observe fosc /32 on pin A_U during calibration mode 2. 2. Use CLOCK(4:0) to tune the oscillator to the desired fcal frequency. (fpinA = fosc /32) 3. Be aware that the oscillator can have as much as 20 % frequency variation over the operating temperature range (-40 C to 125 C). The oscillator runs slower at higher temperatures. To guarantee performance at 125 C it is necessary to tune the oscillator to typ. 12 % higher frequency at room temperature of 25 C.
Theoretical Absolute Accuracy 2.8 5.6 2.8 11.2 5.6 2.8
Accuracy Mode High accuracy Medium accuracy High accuracy Low accuracy Medium accuracy High accuracy
Table 21: Accuracy modes
Description Oscillator frequency System Clock Core Clock Max front-end input frequency Parameter / Condition fosc [Hz] fsystem [Hz] fcore [Hz] ffront [Hz] Requirement or relationship <30 MHz, when VDD = 5 V <25 MHz, when VDD = 3.3 V fsystem = fosc , if CLKDIV = 0 fsystem = fosc /2, if CLKDIV = 1 fcore = fsystem / (1 + FREQ(6:0)) ffront = fsystem / 256, if High Accuracy ffront = fsystem / 128, if Medium Accuracy ffront = fsystem / 64, if Low Accuracy fback = fcore / INTER(7:0) finput = min(ffront , fback ) tedge = 1 / fcore tgran = 1 / fsystem (HYST(1:0) x 1.4 ), if High Accuracy (HYST(1:0) x 2.8 ) if Medium or Low Accuracy tlatency [s] 10 / fsystem [MHz] + 0.2, if no filter 18 / fsystem [MHz] + 0.2, if 8 sample average 26 / fsystem [MHz] + 0.2, if 16 sample average HYST(1:0) FILTER(1:0) Control bit CLOCK(4:0) CLKDIV FREQ(6:0) FREQ(6:0) INTER(7:0)
Max back-end frequency Max iC-TW2 input frequency Min A/B edge separation A/B edge granularity Hysteresis SIN/COS to A/B output latency
fback [Hz] finput [Hz] tedge tgran
INTER(7:0)
Table 22: Configuration dependencies
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 20/30
FREQ(6:0) Code 0x00 f core = f system ... f core = 0x7F f core = HYST(1:0) Code 00 01 10 11 Addr. 0x06; bit 1:0 Function, defaults to eeprom setting no hysteresis 1.4 2.81 5.63 R/W Addr. 0x05; bit 6:0 Function, defaults to eeprom setting R/W
Hysteresis is dependent upon chosen accuracy. The Table below is valid for high accuracy operation.
f system 1 + FREQ(6 : 0) f system 128
Table 25: Master clock divider An averaging filter can be enabled to remove loop instability noise. It is recommended to enable the filter in almost all cases. Enabling the filter increases SIN/COS input to A/B output latency. See Table 22 on page 19 for details.
FILTER(1:0) Addr. 0x06; bit 3:2 Code Function, defaults to eeprom setting 00 01 10 11 filter disabled Average of 8 samples Average of 16 samples undefined R/W
Table 23: Maximum input frequency selection Interpolation setting (register 0x02) in conjunction with the frequency divider (register 0x05) defines the iCTW2's accuracy mode. Table 21 explains the correlation. Based on the selected accuracy mode other system parameters are defined as shown in Table 22. It is recommended to use the divider at all times when support for high input frequencies is not required.
CLKDIV Code 0 1 Addr. 0x0B; bit 1 Function, defaults to eeprom setting fsystem = fosc fsystem = f osc 2 R/W
Table 26: Datapath filter control
Table 24: Master clock divider
DEVICE IDENTIFICATION
IDA(3:0) Code Addr. 0x00; bit 7:4 Function, Major device identification R/W IDB(3:0) Code Addr. 0x00; bit 3:0 Function, Minor device identification R/W
Mask Programmed Value Identifies Major Revision
Mask Programmed Value Identifies Minor Revision
Table 27: Major device revision
Table 28: Minor device revision
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 21/30 START UP Power-On-Reset The iC-TW2 contains a built-in Power-On-Reset (POR) circuitry. The POR keeps the iC-TW2 in reset as long as the applied power supply voltage does not allow reliable operation. Once the power supply ramps up above 1.8 V, the POR releases the reset and the iCTW2 starts the configuration cycle. 20 ms after the device goes out of reset, normal operation begins.
power supply ramp-up reset
True relative operation, A/B phase relation to Z is unknown
A_U B_V Z_W
STARTUP(1:0) = 00
RELATIVE
A_U A/B has known phase relation to Z (same on each B_V startup) Z_W
STARTUP(1:0) = 10
ABSOLUTE
STARTUP(1:0) = 11 A_U Burst output to absolute position B_V within period Z_W
BURST
Volts VDD 3.3 or 5.0 V
Figure 11: Startup behaviour
STARTUP(1:0) Addr. 0x01; bit 4:3 Code Function 00
0.0 V Time 20 ms Power- On- Reset releases, iC-TW2 starts configuration iC-TW2 starts A/B pulse generation. Power supply and sensor input signals should be stable to avoid A/B toggling.
R/W
1.8 V
RELATIVE A/B output signals are kept low during startup. This resembles true relative operation since there is no relationship between A/B levels and sensor position (and therefore Z output) on startup. Reserved ABSOLUTE A/B output signals are phase-related to Z output. A/B output levels are defined by the absolute sensor position within a period. The register IPOS can be used to program the desired A/B to Z phase relationship. BURST The absolute sensor position within the period is output by an A/B burst.
01 10
Figure 10: Power supply ramp-up
11
To avoid A/B output toggling it is important that the power supply and the input signals are stable as soon as normal operation begins. In applications with a slowly rising power supply, it might be necessary to connect an external RC reset to pin NRST to prolong the reset. In applications where startup A/B toggling is acceptable, no precaution must be taken as the iCTW2 will properly power up on an indefinitely slow supply rise time.
Table 29: Startup sequence selection Reset A control bit RESET is provided to block any burst A/B pulses during chip reconfiguration by a microcontroller. While RESET is set A/B/Z output generation is stopped. Access to the interface and register bank is not affected.
RESET Code 0 1 Addr. 0x01; bit 6 Function normal operation default initiate reset R/W
The iC-TW2 startup behaviour is controlled by programming the two control bits STARTUP(1:0) in register 0x01. Three possible startup configurations are allowed, shown in Figure 11. The default behaviour must be specified by the eeprom.
Table 30: Restart interpolation engine
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 22/30 1W- / 2W-INTERFACE AND EEPROM ACCESS Memory map Figure 12 depicts the iC-TW2 memory map and interface diagram. A 2-wire read/write interface and a 1wire write-only interface allow access to the register bank and the EEPROM bank. The register bank is 8 bits wide and it is used to control all chip functionality. Refer to section "Register Map" on page 8 for an overview of all registers. The EEPROM bank on the other hand is 32 bits wide. Address 0x05, 0x06 and 0x07 (3 * 4 bytes = 12 bytes) can be used to store user data such as product serial numbers, calibration and manufacturing information.
1W
1- wire interface write only
SCLK SDAT
2- wire interface read and write
addr 0 addr 1 addr 2 addr 3 addr 4 addr 5 addr 6 addr 7 addr 8 addr 9 addr 10 addr 11 addr 12 addr 13 addr 14 addr 15 Register bank 8 bit wide
addr 0 - reserved addr 1 - reserved addr 2 - reserved addr 3 - reserved addr 4 - reserved addr 5 - user data addr 6 - user data addr 7 - user data EEPROM bank 32 bit wide
Figure 12: Memory map 2W-Interface The first control interface is a standard 2-wire serial interface. It uses an external clock and bidirectional data line. It allows read and write access to all internal registers as well as access to the user EEPROM. The interface consists of two pins, a dedicated input SCLK, the shifting clock and SDAT for bidirectional serial data. The interface handles four types of access requests: 2. Read from control register 3. Write to EEPROM register (including block access and erase) 4. Read from EEPROM register Control register access is shown in Figure 13 (write) and Figure 14 (read) respectively. If SDAT is 00 after the start bit a write access is requested. The data word d(7:0) will be written into register a(4:0). Please note that a(4) is always 0 since the iC-TW2 only has 16 addressable registers.
1. Write to control register
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 23/30
SCLK
SDAT
0
0
a4
a3
a2
a1
a0
d7
d6 8 bit data
d1
d0
0
0
1
SDAT is sampled on falling edge of SCLK 00 indicates write
5 bit address
SDAT is externally driven
extra clocks before new access new access
Figure 13: Register bank write access on 2W-Interface On a register read access the register content is shifted out on SDAT. A read access is indicated by SDAT 10 after the start bit. There is an idle clock required between the last address bit a(0) and the first data bit d(7) returned on SDAT. This clock cycle is used to avoid any bus contention while turning around the bus driver.
SCLK
SDAT 1 0
a4
a3
a2
a1
a0
d7
d6 8 bit data
d0
0
0
1
SDAT is sampled on falling edge of SCLK 10 indicates read
5 bit address
SDAT is externally driven
SDAT is driven by iC-TW2 extra clocks before new access new access
Figure 14: Register bank read access on 2-wire interface Write access to the EEPROM follows the procedure depicted in Figure 15. A start bit is followed by four command bits c-1-e-b. The encoding of the command bits is shown in Table 31. The most useful command is 0100 which performs an erase followed by a write therefore allowing the user to write a new value to the EEPROM with only one interface access.
SCLK
SDAT
c
1
e
b
a2
a1
a0
d31
d30 32 bit data
d1
d0
0
0 20 ms
1
SDAT is sampled on falling edge of SCLK
3 bit address
SDAT is externally driven command select erase control block operation
extra clocks before new access
wait for at least 20ms before any new access
Figure 15: EEPROM write access on 2-wire interface
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 24/30
SCLK
SDAT
1
1
0
0
a2
a1
a0
d31
d30 32 bit data
d0
0
0
1
SDAT is sampled on falling edge of SCLK
3 bit address
SDAT is driven externally
SDAT is driven by iC-TW2 extra clocks before new access new access
Figure 16: EEPROM read access on 2-wire interface The 3 bit address a(2:0) selects the EEPROM register to write to (Figure 12). Each EEPROM register is 32 bits wide, therefore 32 data bits d(31:0) are sent across the interface. At least 20 ms delay is required after every transaction before any new access can start. EEPROM read access is shown in Figure 16. The start bit is followed with the 4 bit read command 1100 and the 3 bit address a(2:0). An idle clock cycle is used to avoid any contention on SDAT while reversing data flow direction. Finally d(31:0) is shifted out on SDAT. EEPROM read access is slow. Please take notice of the timings in Table 32. At least one extra clock with SDAT low is required after every transaction on the 2-wire interface before a new access is started. The interface will not work correctly if this clock cycle is omitted.
EEPROM Commands c 1 e b Description 0 1 0 0 Erase followed by write 0 1 0 1 Block erase followed by block write 0 1 1 0 Block write 0 1 1 1 Read. Please refer to Figure 16 for more details 1 1 0 1 Reserved. Do not use this command 1 1 1 0 Erase 1 1 1 1 Block erase
Purpose Normal EEPROM programming Test only
Test only Special production environment
Table 31: EEPROM Commands 2W-Interface timing The timing of the 2W-Interface is dependent on the type of access performed. Register bank access and EEPROM write access can be performed at full speed. EEPROM read access requires a slow SCLK. Also a 20 ms delay is required after every EEPROM write access before a new transaction of any kind is started (this includes read and write to the register bank).
tsclkH
tsclkL
tsdataS tclk2sdata
tsdataH tclk2sdata
Figure 17: 2W-Interface timing diagram
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 25/30 2W-Interface timing Parameter Description tsclkH SCLK high tsclkL tsdataS tsdataH tsdataH tclk2sdata SCLK low SDAT setup before falling edge of SCLK SDAT setup hold after falling edge of SCLK SDAT setup hold after falling edge of SCLK
Condition EEPROM read access Any other access EEPROM read access Any other access
5 ns
min max 2 s 0 400 ns 2 s 400 ns 100 ns 100 ns 100 ns 100 ns 105 ns
Table 32: 2W-Interface timing
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 26/30 1W-Interface The 1W-Interface provides a write-only access port to the register bank. It is intended as a minimal configuration interface to program the internal EEPROM during in-field service or production. An infrared phototransistor can directly connect to the pin to build a cost effective wireless write port. The input bit stream is pulse-width modulated (or duty-cycle modulated) as shown in Figure 18. A zero-bit is encoded as a short low followed by a long high. A one-bit is encoded as a long low followed by a short high. The modulated signal is independent of the receiver or transmitter clock frequency. Since the iC-TW2 uses a free-running oscillator, it is important to implement a robust, frequencyinsensitive protocol.
idle
0
1
1
0
0
idle
t0low
t0hi
t1low
t1hi
Figure 18: Pulse width modulated bit stream The interface timing is specified in the following Table.
Parameter t0low t0hi t1low t1high Description Low time bit 0 High time bit 0 Low time bit 1 High time bit 1 min 40 s 120 s 120 s 40 s max 100 s 200 s 200 s 100 s
1W- / 2W-Interface is allowed or data corruption might occur. 3. Finally the register content, after a device reset and configuration, should be verified to ensure a successfull EEPROM write sequence. Writing the registers to the EEPROM using EE_WRITE takes up to 100 msec. During this access to the register bank either through the 1W- or 2W-Interface is prohibited. Any access will corrupt data written to the EEPROM.
EE_WRITE Addr. 0x0E; bit 6 W Code Function, bit is automatically reset upon completion of operation 0 1 Normal operation (default) Store registers into EEPROM
Table 33: 1W-Interface timing 1W-Interface write sequence Figure 19 describes the write sequence to the register bank, which uses the same protocol as the 2WInterface. On an idle wire, a write sequence is initiated by writing a start bit (1) followed by the write command (00) followed by the address and register data. At the end of the sequence, a stop-bit (0) is required. 1W-Interface write access to the EEPROM bank is shown in Figure 20. The 4 bit EEPROM command after the start bit is decoded in Table 31. Writing the register bank to the EEPROM To permanently store a configuration in the internal EEPROM the following procedure should be followed.
Table 34: EEPROM store command
idle
1
0
0
address(4:0)
data(7:0)
0
idle
Start Write to Register bank Bit Regbank address
8 bit register data
Stop Bit
1. The 1W- / 2W-Interface is used to fully write the desired configuration into the register bank. 2. A logic one is written to bit EE_WRITE of register 0x0E. This will initiate a write sequence which copies all registers into the internal EEPROM. A complete write takes 100 ms. During this time, no access to the register bank through either the
Figure 19: 1W-Interface register bank write sequence
idle
1
c
1
e
b
address(2:0)
data(31:0)
0
idle
Start Bit
EEPROM command
EEPROM bank address
32 bit EEPROM data
Stop Bit
Figure 20: 1W-Interface EEPROM write sequence
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 27/30 TEST MODES The iC-TW2 provides various control bits located in different registers to enable or disable certain test modes. The majority of these is only required for extended chip testing capability, others are required for production test.
GRANULAR Code 0 1 Addr. 0x05; bit 7 Function, test mode only normal operation test mode only R/W MONITOR(7:0) Addr. 0x0F; bit 7:0 Code Function R/W EN_MON Code 0 1 Addr. 0x0B; bit 3 Function Position monitor disabled default Monitor enabled R/W
Table 39: Position monitor control
Access to the internal absolute period position. RT only!
Table 35: A/B output edge granularity control Table 40: Monitor register
VC(1:0) Code Addr. 0x0A; bit 6:5 Function, test mode only register must be set to 0 for correct device functionality R/W EE_READ Code 0 1 Addr. 0x0E; bit 7 Function Normal operation Read all iC-TW2 registers from the EEPROM. Bit is automatically reset upon completion. Not required during normal operation since this is done automatically on start-up. W
Table 36: Reference voltage fine tuning
CLKMODE Addr. 0x0B; bit 0 Code Function, test mode only 0 1 Select comparator clock default Select direct oscillator clock R/W
Table 41: EEPROM read command register Production test control bits Production test control bits are reserved bits. Do not use the production test control bits during normal operation. Keep reserved bits "0".
Reserved Reserved Reserved Code 0 1 ... Addr. 0xC; bit 7:1 Addr. 0xD; bit 7:0 Addr. 0xE; bit 2:0 Function Normal operation Do not use or alter to R/W R/W R/W
Table 37: Clock source select
CLKDLY Code 0 1 Addr. 0x0B; bit 2 Function Normal operation Add clock delay R/W
Table 38: Clock distribution delay line selection Enabling the position monitor will allow access to the internal absolute period position. The position can be read through register 0x0F. This is considered a test mode and should not be used during normal operation.
Table 42: Test modes
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 28/30 TYPICAL APPLICATIONS The circuit in Figure 21 depicts a typical application. Differential sensor signals (or differential SIN / COS encoder signals) are directly connected to the iC-TW2. Index gating is single ended active low as is frequently the case when using a HALL switch. The VC signal of 1.21 V is used to bias the positive input PINZ. It is recommended to decouple VC with a small capacitor when it is used as a reference. When VC is left unconnected, no capacitor is required.
Figure 21: Example of application circuit with differential sensor and single ended index gating
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 29/30 PCB LAYOUT GUIDELINES The iC-TW2 is a noise sensitive mixed signal device, which requires careful PCB layout considerations. Violating the layout guidelines can result in poor performance. Please consider Figure 22 . Power pins VDDA (pin 10) and VDD (pin 1) must be decoupled with 1 F. Trace length to VDD pins must be no longer than 3 mm. The decoupling caps can be placed on the bottom side of the PCB directly connecting it to the iC-TW2 pads using vias. Ground pins GND (pin 6) and GNDA (pin 11) must be tied to the center exposed pad. The exposed pad is then directly connected to the PCB ground plane using several vias.
VSS pin 6 and 11 tied to exposed pad. EP strapped to ground plane using several vias .
1 F C603
Max 3 mm from VDD pin 1 and 10 to 1 F decoupling caps.
1 F C603
Figure 22: PCB layout guidelines
iC-Haus expressly reserves the right to change its products and/or specifications. An Infoletter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying - even as an excerpt - is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
iC-TW2 8-BIT SIN/COS INTERPOLATION IC
WITH INTEGRATED EEPROM
Rev D3, Page 30/30 ORDERING INFORMATION
Type iC-TW2 Evaluation Board
Package 24 pin QFN, 4 mm x 4 mm PCB 100 mm x 80 mm
Order Designation iC-TW2 QFN24 iC-TW2 EVAL TW2_2D
For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel.: +49 (61 35) 92 92-0 Fax: +49 (61 35) 92 92-192 Web: http://www.ichaus.com E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners

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